1. Field of the Invention
The present invention relates to an image processing apparatus and an image processing method and, more particularly, to an image processing apparatus and an image processing method in which a function is performed to freely deform a two-dimensional image data.
2. Description of the Related Art
Conventionally a two-dimensional graphic is displayed in a definite form. However, the need of free deformation of the two-dimensional graphic is increased in conjunction with a technical development with regard to a graphic process.
FIG. 1 is a block diagram showing the structure of a conventional two-dimensional image processing apparatus. The two-dimensional image processing apparatus is composed of a CPU 11, and a two-dimensional (2D) graphic processor 12 connected to the CPU 11. A figure ROM 13 and a display buffer section 14 are connected to the 2D graphic processor 12. The 2D graphic processor 12 is composed of a DATA I/F section 15, an object table section (hereinafter, to be referred to as an OBJ table section) 16, an FI/FO section 17 composed of first-in first-out registers, a timing signal generating section 19, a ROM address adder 20, a ROM address generating counter 21 and a display buffer section address adder 22.
FIG. 2 is a flowchart showing an operation of the conventional two-dimensional image processing apparatus. When the CPU 11 sends a CPU data signal S3 to the DATA I/F section 15, the DATA I/F section 15 outputs an OBJ table section setting data signal S4 to the OBJ table 16 to set a record of display parameters of respective figures (Step S1), if the CPU data signal S3 is a signal to be directed to the OBJ table 16. An X coordinate origin value P1, a Y coordinate origin value P2 and a display figure ROM origin value P3 are given as the display parameters of the OBJ table 16. On the other hand, the DATA I/F section 15 outputs an FI/FO setting data signal S5 to the FI/FO section 17 to set OBJ addresses PA included in the signal S5, if the CPU data signal S3 is a signal to be directed to the FI/FO section 17.
The FI/FO section 17 switches an FI/FO section empty signal S8 directed to the timing signal generating section 19 from a disable state to an enable state at a time point when the OBJ addresses PA are set therein. Accordingly, the timing signal generating section 19 is initialized to be set to a drawing state. In this state, the timing signal generating section 19 and the display buffer section 14 are set to an active state in response to a vertical synchronous signal S1. At that time, if the FI/FO section empty signal S8 is in the disable state, the 2D graphic processor 12 does not operate until a next horizontal synchronization signal S2 is inputted. If the FI/FO section empty signal S8 is in the enable state, when the timing signal generating section 19 outputs an FI/FO section request signal S7 to the FI/FO section 17 in response to the horizontal synchronous signal. The FI/FO section 17 outputs an OBJ table section address signal S6 to the OBJ table 16 in response to the FI/FO section request signal S7 to read out the parameters of the figure data to be displayed (Steps ST2 to ST4).
After the respective parameters of the figure data are outputted from the OBJ table 16, the timing signal generating section 19 outputs a ROM calculation control signal S21 to the ROM address generating counter 21. The ROM address generating counter 21 receives the ROM calculation control signal S21 as a start signal, and then generates and outputs a ROM address generating counter output signal S13. On the other hand, the ROM address adder 20 adds the ROM address generating counter output signal S13 and the display figure ROM origin value P3 included in a figure ROM address origin signal S11 supplied from the OBJ table 16 to generate and output a figure ROM address signal S12 to the figure ROM 13 (Step S5).
The figure ROM 13 outputs a display buffer section data signal S15 having a desired figure data to the display buffer section 14 based on the figure ROM address signal S12. At the same time, the display buffer section address adder 22 adds the ROM address generating counter output signal S13 and each of the X coordinate origin value P1 included in an X coordinate origin signal S9 supplied from the OBJ table 16 and the Y coordinate origin value P2 included in a Y coordinate origin signal S10 to determine a display position where the figure is to be displayed, and then outputs a generated display buffer section address signal S17 to the display buffer section 14.
While the display buffer section data signal S15 and the display buffer section address signal S17 are outputted, a display buffer enable signal S16 supplied from the ROM address generating counter 21 is switched from the disable state to the enable state. Thus, the figure data is stored in the display buffer section 14 in accordance with the display positions of the figure data.
The timing signal generating section 19 determines the state of the FI/FO section empty signal S8 sent from the FI/FO section 17. The timing signal generating section 19 repeats this operation until this signal S8 is switched to the disable state. Also, the figure data sent from the figure ROM 13 is stored in the display buffer section 14. At a time point when all the pixel data of a single figure for the horizontal line is stored in the display buffer section 14, the display buffer enable signal S16 is switched from the enable state to the disable state. Thus, the operation for the horizontal line is ended (Step ST6). The above operation is repeated for all the horizontal lines.
Next, all the data stored in the display buffer section 14 are outputted to a display device (not shown). Through the repetition of the above mentioned operation, the figure data can be displayed on the screen.
A procedure when a display figure example 1 (sp1) and a display figure example 2 (sp2) are set to be displayed on the screen as a display screen example 1 (SC1), and the display figure examples 1 and 2 are deformed as shown as a display screen example 2 (SC2), a display screen example 3 (SC3) and a display screen example 4 (SC4) in this order will be described below. FIGS. 3A to 3D show the display figure example 1 (sp1) on the coordinates (x1,y1) of the display screen and the display figure example 2 (sp2) on the coordinates (x2,y2). FIG. 4 is a schematic diagram showing the content of a conventional figure ROM mapping.
In a display screen example 1 (SC1) of FIG. 3A, a figure ROM data 1 (RD1) mapped into an address R1(h) of the figure ROM 13 shown in FIG. 4 is displayed as a display figure example 1 (sp1), and a figure ROM data 2 (RD2) mapped into an address R2(h) is also displayed as a display figure example 2 (sp2). For example, when the respective parameters of the display figure example 1 (sp1) are to be set in an address a(h) of the OBJ table 16, the CPU 11 sets x1(h) to the X coordinate origin value P1, y1(h) to the Y coordinate origin value P2, and R1(h) to the display figure ROM origin value P3, respectively. Also, when the respective parameters of the display figure example 2 (sp2) are set in an address b(h) of the OBJ table 16, the CPU 11 sets x2(h) to the X coordinate origin value P1, y2(h) to the Y coordinate origin value P2 and R2(h) in the display figure ROM origin value P3, respectively. Moreover, the CPU 11 sets the addresses a(h) and b(h) of the OBJ table 16 to the FI/FO section 17. Thus, the display screen example 1 (SC1) can be displayed on the screen through the above mentioned operation.
When the display figure example 1 and the display figure example 2 are deformed as shown as the display screen example 2 (SC2) in FIG. 3B, the figure ROM data 3 (RD3) is mapped into an address R3(h) of the figure ROM 13, and the figure ROM data 4 (RD4) is mapped into an address R4(h) such that they are used as the display figure example 3 (sp3) and the display figure example 4 (sp4). At that time, the CPU 11 sets R3(h) to the display figure ROM origin value P3 of the OBJ table 16 when setting the display figure example 3 (sp3) in the address a(h) of the OBJ table 16. Also, the CPU 11 sets R4(h) to the display figure ROM origin value P3 of the OBJ table 16 when setting the display figure example 4 (sp4) in the address b(h). Next, the CPU 11 sets the addresses a(h) and b(h) of the OBJ table 16 to the FI/FO section 17, respectively. Thus, the display screen example 2 (SC2) is displayed on the screen through the above mentioned operation.
Also, when the display figure example 3 and the display figure example 4 are deformed as shown as the display screen example 3 (SC3) in FIG. 3C, a figure ROM data 5 (RD5) is mapped into an address R5(h) of the figure ROM 13 and a figure ROM data 6 (RD6) is mapped into R6(h) of the figure ROM 13 such that they are used as the display figure example (sp5) and the display figure example (sp6). At that time, the CPU 11 sets the R5(h) to the display figure ROM origin value P3 of the OBJ table section 16 when setting the display figure example 5 (sp5) in the address a(h) of the OBJ table 16. Also, the CPU 11 sets the R6(h) to the display figure ROM origin value P3 of the OBJ table 16 when setting the display figure example 6 (sp6) in the address b(h). Next, the CPU 11 sets the addresses a(h) and b(h) of the OBJ table 16 to the FI/FO section 17, respectively. Thus, the display screen example 3 (SC3) is displayed on the screen through the above mentioned operations.
Moreover, when the display figure example 3 and the display figure example 4 are deformed as shown as the display screen example 4 (SC4) in FIG. 3D, a figure ROM data 7 (RD7) is mapped into an address R7(h) of the figure ROM 13 and a figure ROM data 8 (RD8) is mapped into R8(h) of the figure ROM 13 such that they are used as a display figure example 7 (sp7) and a display figure example 8 (sp8). At that time, the CPU 11 sets the R7(h) to the display figure ROM origin value P3 when setting the display figure example 1 (sp1) in the address a(h) of the OBJ table 16, and sets the R8(h) to the display figure ROM origin value P3 when setting the display figure example 2 (sp2) in the address b(h). Next, the CPU 11 sets the addresses a(h) and b(h) of the OBJ table 16 to the FI/FO section 17, respectively. Thus, the display screen example 4 (SC4) is displayed on the screen through the above mentioned operations.
As mentioned above, in the conventional two-dimensional image processing apparatus, the deformation of the figure is performed while the figure data in a fixed form is set at a specified coordinate position at each time. Therefore, a figure corresponding to any figure data other than the figure data stored in the figure ROM 13 cannot be processed. Also, the figure data after the deformation must be all stored in the figure ROM 13. Thus, the ROM capacity necessary for the figure data after the deformation is extremely large.